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Device Overview S12XS Family
1.2.3
1.2.3.1
Detailed Signal Descriptions
NOTE
The pin list of the largest package version of each S12XS Family derivative
gives the complete of interface signals that also exist on smaller package
options, although some of them are not bonded out. For devices assembled
in smaller packages all non-bonded out pins should be con?gured as outputs
after reset in order to avoid current drawn from ?oating inputs. Refer to
Table 1-6 for affected pins.
EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the oscillator output.
1.2.3.2
RESET — External Reset Pin
The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a
known start-up state. As an output it is driven low to indicate when any internal MCU reset source triggers.
The RESET pin has an internal pull-up device.
1.2.3.3
TEST — Test Pin
This input only pin is reserved for factory test. This pin has a pull-down device.
NOTE
The TEST pin must be tied to V SS in all applications.
1.2.3.4
BKGD / MODC — Background Debug and Mode Pin
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has an internal pull-up device.
1.2.3.5
PAD[15:0] / AN[15:0] — Port AD Input Pins of ATD0
PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital
converter ATD0.
1.2.3.6
PA[7:0] — Port A I/O Pins
PA[7:0] are general-purpose input or output pins.
1.2.3.7
PB[7:0] — Port B I/O Pins
PB[7:0] are general-purpose input or output pins.
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
41
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